module STACK(clk,reset, aluStackPop,chrStackPush,chrStackData,fsmStackClear,
	     stackAluData,SpyStackData);

input aluStackPop,chrStackPush,fsmStackClear;
input reset,clk;
//I do not know how to use 'fsmStackClear' this parameter
input [16:0] chrStackData;
output reg [16:0] stackAluData;
output wire [16:0] SpyStackData;


reg [16:0] ram [3:0];


assign SpyStackData = ram[0];

always @(posedge clk)
         if(reset)
                 begin
                    stackAluData<=17'b0;
						  ram[3]<=17'b0;
						  ram[2]<=17'b0;
						  ram[1]<=17'b0;
						  ram[0]<=17'b0;

                end
          else
                case({aluStackPop,chrStackPush})
                        2'b01: begin
                                ram[3]<=ram[2];
                                ram[2]<=ram[1];
											ram[1]<=ram[0];
                                ram[0]<=chrStackData;
                                 end
                        2'b10: begin
                                stackAluData<=ram[0];
										  ram[0]<=ram[1];
										  ram[1]<=ram[2];
                                ram[2]<=ram[3];  
											ram[3]<=17'b0;
                                end
                        default:;
                endcase
endmodule
